Axelera AI unveils titania data center AI chip architecture, targeting 2027 q3 production

Dutch semiconductor startup Axelera AI revealed the architecture for its third-generation AIPU chip, Titania, on November 12th. This chip is aimed at the data center inference market and is slated for mass production in the third quarter of 2027. The company has already secured orders exceeding $300 million for the new hardware. Titania features a power consumption of 400W and comprises two compute chiplets built on a third-generation D-IMC architecture. It is optimized for sparse MoE models, supporting MXPF4 and MXFP8 data formats, achieving a peak FP8 compute capacity of 2.5 PFLOPS, and integrating a 128MB shared SRAM cache. The design also incorporates 32 RISC-V cores for offloading host CPU tasks, alongside multi-format codecs like AV1 and H.265. Further specifications include the integration of 128GB of LPDDR6 memory, providing a total bandwidth of 2456GB/s, and support for PCIe AIC and OCP OAM form factors. Axelera AI claims that a 4U, eight-card Titania air-cooled server can locally run a 1.6T MoE model at FP4 precision, potentially delivering seven times the per-watt throughput and one-twentieth the total cost of ownership compared to current data center servers.